A cache coherence protocol can be implemented in a multiprocessor system. For example, a multiprocessor system can include a plurality of processors (e.g., a plurality of cores), a plurality of controllers and a plurality of cache memories. Each of the plurality of processors can be associated with a controller that manages content in a cache memory. For example, a controller can manage a cache memory so that the cache memory includes a most recent copy of data (e.g., a copy of data that matches data in a main memory of the multiprocessor system). The cache coherence protocol can include a snooping mechanism. For example, snoop messages can be sent between the plurality of controllers in the multiprocessor system to achieve cache coherency. Furthermore, the plurality of processors can be enabled and disabled based on power requirements and/or performance requirements of the multiprocessor system. Accordingly, the multiprocessor system can be dynamically scaled based on power requirements and/or performance requirements of the multiprocessor system.
However, in a snoop-based multiprocessor system, dynamic scaling can make cache coherence difficult since the number of coherent (e.g., enabled) controllers changes over time. Furthermore, dynamic scaling can make cache coherence difficult since the number of snoop messages and/or the number of acknowledgment messages required for implementing a cache coherence snooping protocol changes over time. Therefore, snoop messages are often broadcast to all controllers in a multiprocessor system. As such, at least a portion of a controller is required to be powered-up at all times in order to respond to the snoop messages.
The above-described description is merely intended to provide a contextual overview of current multiprocessor systems and is not intended to be exhaustive.